The tremendous advancement of electronic industry leads electronic products to develop with multi-functionality and high performances to satisfy the packaging requirements such as high integration and miniaturization for semiconductor packages. In order to improve the performance and capacity of a single semiconductor package for use in a miniaturized electronic product with large capacity and high speed, the semiconductor package is conventionally made in the form of a MCM (multi chip module), which can reduce the overall volume and improve the electrical performance of the package and thus becomes a primary type of package in the industry. In the MCM structure, at least two semiconductor chips are mounted on a chip carrier and each of the chips is stacked on the chip carrier in a vertical manner.
A conventional chip-stacked structure allows a lower chip to be electrically coupled to a substrate by a flip-chip technique, and an upper chip to be electrically coupled to the substrate by a wire-bonding technique. Such packaging technology is disclosed in U.S. Pat. Nos. 5,815,372 and 6,462,405 shown in FIGS. 1 and 2 respectively, and is briefly described as follows.
FIG. 1 shows a conventional stacked-type ball grid array (BGA) chip package structure. As shown, this chip package structure includes: a substrate 100 having a front surface 100a and a back surface 100b; a first chip 110 having an active surface 110a and a non-active surface 10b, wherein the active surface 110a of the first chip 110 is electrically coupled to the front surface 100a of the substrate 100 by solder bumps 111 in a flip-chip manner; a second chip 120 having an active surface 120a and a non-active surface 120b, wherein the non-active surface 120b of the second chip 120 is attached to the non-active surface 10b of the first chip 110 by an adhesive layer 121; a plurality of conductive wires 140 formed from the active surface 120a of the second chip 120 to the front surface 100a of the substrate 100, for electrically coupling the second chip 120 to the substrate 100; an encapsulant 150 for encapsulating the two stacked chips 110, 120; and a ball grid array 160 implanted on the back surface 100b of the substrate 100, for serving as external electrical contacts of the package unit.
However, the foregoing stacked-type BGA chip package structure has a drawback that a large amount of heat is produced along with the operation of the highly integrated chips, and the encapsulant for encapsulating the chips is made of a poor thermally conductive resin material with a coefficient of thermal conductivity of only 0.8 w/m-k, thereby resulting in unsatisfactory heat dissipating efficiency and affecting the performances and lifetime of the chips. In other words, as there is no heat dissipating structure provided for the packaged chips 110, 120, the heat produced during practical operation of the chips 110, 120 is accumulated between the chips 110, 120, and the heat produced by the lower chip 110 is transferred to the upper chip 120, making the upper chip 120 easier to be damaged by thermal stress.
FIG. 2 shows a conventional stacked-type BGA chip package structure with a heat dissipating structure. As shown, this chip package structure is substantially the same as that shown in FIG. 1, with a primary difference in that a heat sink 230 is provided on the substrate 100 to enhance the heat dissipating efficiency of the package structure. The heat sink 230 comprises a supporting portion 231 and a top portion 232, wherein the supporting portion 231 is supported on the front surface 100a of the substrate 100, and the top portion 232 is disposed above the upper chip 120. By this arrangement, the heat produced during the practical operation of the chips 110, 120 is firstly transferred to the resin material located between the second chip 120 and the heat sink 230 and then dissipated out of the package structure by the heat sink 230. Therefore, the package structure shown in FIG. 2 has better heat dissipating efficiency than that shown in FIG. 1.
However, in practical implementation, as the heat sink 230 of the package structure shown in FIG. 2 is not directly in contact with the non-active surfaces 110b, 120b of the two chips 110, 120, the heat produced by the chips 110, 120 must be transferred through the resin material with poor thermal conductivity to the heat sink 230, thereby not able to provide satisfactory heat dissipating efficiency.
Referring to FIG. 3, in view of the drawbacks in the foregoing conventional technology, U.S. Pat. No. 6,472,741 discloses a thermally enhanced stacked-type BGA chip package structure, comprising: a substrate 300 having a front surface 300a and a back surface 300b; a first chip 310 having an active surface 310a and a non-active surface 310b, wherein the active surface 310a of the first chip 310 is electrically coupled to the front surface 300a of the substrate 300 in a flip-chip manner; a heat sink 338 comprising a supporting portion 330, a top portion 337 and a bottom portion 339, wherein at least one wire-routing hole 336 is formed in the top portion 337, the supporting portion 330 of the heat sink 338 is mounted on the front surface 300a of the substrate 300, and the bottom portion 339 is attached to the non-active surface 310b of the first chip 310 in a thermally conductive manner; a second chip 320 having an active surface 320a and a non-active surface 320b, wherein the non-active surface 320b of the second chip 320 is attached to the top portion 337 of the heat sink 338 in a thermally conductive manner; a plurality of conductive wires 340 formed from the active surface 320a of the second chip 320, through the wire-routing hole 336 in the top portion 337 of the heat sink 338, to the front surface 300a of the substrate 300, for electrically coupling the second chip 320 to the substrate 300; an encapsulant 350 for encapsulating the front surface 300a of the substrate 300, the first chip 310, the heat sink 338, the second chip 320 and the conductive wires 340; and a plurality of solder balls 360 implanted on the back surface 300b of the substrate 300. By direct contact of the top portion 337 and the bottom portion 339 of the heat sink 338 with the non-active surfaces 320b, 310b of the two chips 320, 310 respectively, better heat dissipating efficiency can be achieved by this package structure as compared to the conventional technology shown in FIG. 2.
In line with the requirements such as compact profiles and high performances for the electronic products, the semiconductor package structure is correspondingly sized smaller and smaller, such that a CSP (Chip Scale Package) structure e.g. a TFBGA (Thin and Fine-Pitch Ball Grid Array) package is developed and becomes widely demanded. However in the CSP structure, since the substrate has a size nearly equal to the size of the chip and the area for bonding the conductive wires is limited to a portion between the chip attach area and edges of the substrate, there is no space on the substrate available for receiving a supporting portion of a heat sink. Under this situation, the heat sink with the supporting portion used in the foregoing U.S. Pat. No. 6,472,741 cannot be applied to the CSP structure or a substrate with a high-density circuit layout. Moreover, to accommodate the supporting portion of the heat sink on the substrate also causes a trouble in the manufacture of the substrate.
Accordingly, U.S. Pat. No. 6,472,743 discloses a package structure with solder balls being provided at corners of a substrate to serve as supporting portions for a heat sink. However, this arrangement requires corresponding modification of the substrate structure, and also easily causes slanting of the heat sink mounted on the solder balls due to difficulty in controlling the height of the solder balls. The slanted heat sink may possibly come into contact with signal wires of the chip and thereby results in a short-circuiting problem. This as a result leads to inconvenience in the fabrication processes, degraded reliability and increased costs. And similarly, to accommodate the supporting portions (solder balls) for the heat sink on the substrate causes a trouble in the manufacture of the substrate.
Further in the foregoing semiconductor packages, the attachment between the heat sink and the chip needs to be precisely controlled to avoid slanting of the heat sink, such that a batch-type method cannot be used to attach heat sinks to chips. That is, the heat sinks must be adhered to the corresponding chips one by one, thereby increasing the complexity and time of the overall packaging processes, which is undesirable for reducing the packaging costs and improving the packaging efficiency.